1. Field of the Invention
The present invention relates to a Delta-Sigma AD converter that is utilized, e.g. in radio receivers requiring high-speed clock operation and a high SNR (Signal to Noise Ratio).
2. Description of Related Art
Conversion of analog signals into digital signals makes easy and efficient signal transmission and processing possible. Accordingly, analog-to-digital (AD) converters are an important feature in radio receivers used in mobile phones etc. As a result of the increased data speeds associated with the increase in the broadband capabilities of communication systems in recent years, there is a need to simultaneously implement low power consumption, high-speed clock operation, and high SNRs in AD converters. For this reason, efforts have continued to be made in order to increase the operating clock speed in Delta-Sigma AD converters, which were originally used in measuring equipment and which make it possible to easily achieve a high SNR.
FIG. 13 is a block diagram showing an example of a conventional n-th order Delta-Sigma AD converter (see FIG. 1 of JP2005-72632A). This n-th order Delta-Sigma AD converter is composed of integrators 30[0]-30[n], subtractors 31[0]-31[n], input circuits 32[0]-32[n], feedback circuits 33[0]-33[n], a quantizer 34, and a digital-to-analog converter 35. It has a closed loop configuration, in which the digital output of the quantizer 34 is converted to an analog quantity by the digital-to-analog converter 35 and fed to the subtractors 31[0]-31[n] via the feedback circuits 33[0]-33[n]. A difference between the output signals of the input circuits 32[0]-32[n] and the output signals of the feedback circuits 33[0]-33[n] is obtained by the subtractors 31[0]-31[n] and their output signals are input, respectively, to the integrators 30[0]-30[n]. 
The integrators 30[0]-30[n] possess low-pass filter characteristics, whereby they pass only low-frequency components and block high-frequency components. For this reason, when the above-described AD converter configuration is used, the action of the analog integrators 30[0]-30[n] on the quantization noise generated by the quantizer 34, which is a type of white noise independent of the frequency characteristic, causes low-frequency noise power to shift towards higher frequencies and reduces noise power in the signal frequency band. This effect is generally known as the “noise-shaping effect”.
Here, in a first-order integrator, the amount of attenuation of noise power at low frequencies reflects a first-order noise shaping effect (20 dB/dec) and, in an n-th order integrator, it reflects an n-th order noise shaping effect (n×20 dB/dec). Therefore, in terms of implementing a high SNR, it becomes advantageous to increase the number of integrators and increase the filter order.
However, increasing the number of integrators leads to increased power consumption and, in case of portable radios, creates problems in practical use.
To eliminate such problems, a method has been proposed, in which integrators are multiplexed and a filter characteristic equivalent to n integrators is attained in a single integrator (e.g. see ISSCC 2005, Session 9/9.3, “A 66 dB DR 1.2V 1.2 mW Single-Amplifier Double-Sampling 2nd-order ΔΣ ADC for WCDMA in 90 nm CMOS”).
FIG. 14 is a block diagram schematically illustrating a sigma-delta AD converter obtained when 2nd-order integrators are multiplexed. In the configuration of FIG. 14, a signal from an input circuit 32 is input to a subtractor 31 and, along with that, two outputs from an integrator 30, one that is 1 sample behind (unit delay) and another one from a sampling instant, are fed back by a feedback circuit 36 to the subtractor 31 at the input of the integrator 30. Furthermore, outputs from a digital-to-analog converter 35, one that is 1 sample behind (unit delay) and another one from a sampling instant, are fed back by feedback means 37 to the subtractor 31 at the input of the integrator 30. As a result, a low-pass filter characteristic equivalent to a configuration with two integrators is provided without multiplexing the integrator 30. Other configurations are similar to the conventional example of FIG. 13.
Furthermore, the feedback circuit 36 is configured to have n integrator outputs ranging from n samples behind (n-sample delay) to the sampling instant, the feedback circuit 37 is configured to have n digital-to-analog converter outputs from n samples behind (n-sample delay) to the sampling instant, and, in a similar manner, the outputs can be fed back to the subtractor 31 at the input of the integrator. As a result, it becomes possible to provide a low-pass filter characteristic equivalent to a configuration with n integrators, improve integrator power consumption, and achieve a high SNR based on an n-th order noise-shaping effect.
However, to obtain an n-th order noise-shaping effect in the conventional multiplexing circuit system shown in FIG. 14, it is necessary to use a configuration, in which the n feedback circuits constituting the feedback circuit 36 are connected in parallel to the I/O terminals of the integrator 30 and the n feedback circuits constituting the feedback circuit 37 are connected in parallel to the input of the integrator 30, and, furthermore, to operate the circuitry of all the feedback circuits 36 and 37 during each sampling time interval. Accordingly, the load connected to the I/O of the integrator 30 increases in comparison with the case shown in FIG. 13, in which integrators are not multiplexed.
Generally speaking, in an integrator, its characteristics, in particular its settling time and stability, will deteriorate if the current consumption of the integrator is not increased in proportion to an increased load. For this reason, the problem is that when n integrators are multiplexed and operated using a single integrator in a configuration such as the one shown in FIG. 14, the current consumption of the single integrator is increased and the current consumption-reducing effects resulting from integrator multiplexing are decreased.